7.2 Transfer registers

7.2.1 FIFO Violation Event Register (FWEV)

TXWARN. Transmission disruption warning. Set to "1" when the corresponding transmitting FIFO endpoint has exceeded the limit defined by the TFWL bit in the TXCx register and transmission from the corresponding endpoint is enabled. This bit is cleared when the violation warning condition is cleared, either by writing new data to the FIFO when the FIFO is cleared, or upon completion of the transfer, as indicated by the TX_DONE bit in the TXSx register.

RXWARN. Reception warning. Set to "1" when the corresponding transmitting FIFO endpoint has exceeded the limit specified by the RFWL bit in the EPCx register. This bit is cleared when the violation warning condition is cleared, either by reading data from the FIFO or when the FIFO is cleared.

7.2.2 FIFO Violation Mask Register (FWMSK)

When the corresponding bit in the FWEV register is set, WARN in the MAEV register is set. When cleared, the corresponding bit in the FWEV register does not cause WARN to be set.

7.2.3 Frame Number Significant Register (FNH)

FN. Frame number. This is the current received frame number in the last SOF packet. If the correct frame number is not received during the 12060 bits (maximum frame length, FLMAX) of the previous exchange, then the frame number is artificially increased. If two consecutive frames are missed or incorrect, the current FN is frozen and loaded with the frame number from the SOF packet.

If the low byte of the frame number was read by the firmware before reading the FNH register, then the user is actually reading the contents of the buffer register, which contains the value of the three frame number bits of that register when the low byte was read. The correct sequence to read the frame number is: FNL, FNH. Read operations for the FNH register, without first reading the Frame Number Low Byte (FNL) register, read the actual value of the three least significant bits into the frame number. Upon reset, FN is set to "0".

RFC. Reset frame counter. Setting this bit resets the frame number to 0x0000, after which this bit clears itself. This bit is always read as "0".

UL. Unlock flag. This bit indicates that at least two frames were received without the expected frame number, or that a valid SOF was not received within 12060 bits of arrival time. If this bit is set, then the frame number from the next valid packet is loaded into the FN. When reset, this flag is set to "1".

M.F. Lost SOF flag. This bit is set when the frame number in the received SOF packet is not equal to the expected value, or when SOF is not received within 12060 bits of arrival time. When reset, this flag is set to "1".

7.2.4 Frame Number Low Byte Register (FNL)

This register contains the low byte of the frame number, as described above. To ensure consistency, reading this low byte causes the three frame number bits in the FNH register to be latched while the register is read. The correct sequence for reading the frame number is: FNL, FNH. Upon reset, FN is set to "0".

7.2.5 Functional Address Register (FAR)

This register sets the functional address of the device. The different endpoint numbers are set individually via the endpoint control register.

A.D. Address. This field contains the 7-bit functional address used to send and receive all characters addressed to the device.

AD_EN. Addressing resolution. When the bit is set to "1", bits AD6-0 are used in address comparison (see Section 6.2 for details). When cleared, the device does not respond to any character on the bus.

Note: If the DEF bit in the checkpoint 0 control register is set, then endpoint 0 responds to its default address.

7.2.6 DMA Control Register (DMACNTRL)

DSRC. DMA source. The DMA Source bits field contains a binary value that determines which of the endpoints, 1...6, are available to support DMA. DSRC bits are cleared on reset. Table 7 shows the DSRC bit settings.

Table 7. Description of DSRC bits

DMOD. DMA mode. This bit determines when a DMA request occurs. If it is cleared, the DMA request appears when the transfer is completed. For transmitting endpoints EP1, EP3 and EP5, the data is fully transmitted, as indicated by the TX_DONE bit (to fill the FIFO with new transmitted data). For receiving endpoints EP2, EP4 and EP6, this is reflected by the RX_LAST bit. When the DMOD bit is set, a DMA request occurs when the corresponding FIFO violation warning bit is set. The DMOD bit is cleared on reset.

The DMA request from the sending endpoint is activated until the request state is cleared. If DMOD is set to "0", then DMA requests occur either until the firmware reads the corresponding transmit status register (TXSx), thereby clearing the TX_DONE bit, or if the TX_LAST bit in the transmit command register (TXCx) installed by hardware-implemented software. If the DMOD bit is set to "1", then DMA requests occur until FIFO violation warning states caused by either sending enough bytes to the endpoint or if the TX_DONE bit is set due to a transfer are cleared.

The DMA request from the sending endpoint is activated until the request state is cleared. If DMOD is set to "0", then DMA requests occur either until the firmware reads the corresponding receive status register (RXSx), thereby clearing the RX_LAST bit, or if the FIFO becomes empty due to enough cycles reading. If the DMOD bit is set to "1", then DMA requests occur until the FIFO violation warning states are cleared or the FIFO endpoint becomes empty due to enough read cycles.

If DMOD is set to "0" and the endpoint and DMA are enabled, then a DMA request occurs as long as the firmware reads the corresponding TXSx or RXSx register, thereby clearing the TX_DONE/RX_LAST bit. If the DMOD bit is set to "1" and the endpoint and DMA are enabled, then the DMA request occurs as long as the FIFO violation alert states.

ADMA. Automatic DMA. Setting this bit automatically enables the selected receive or transmit endpoint. Before enabling ADMA mode, the DEN bit in the DMA Control Register (DMACNTRL) must be cleared. ADMA mode operates as long as any bit other than NTGL in the DMA Event Register (DMAEV) is set. To initialize ADMA mode, all bits except NTGL in the DMAEV register must be cleared.

For receive operations, the receiver is turned on automatically; When a packet is received, it is transferred via DMA to memory.

For transfer operations, the data packet is sent via DMA from memory; the transmitter turns on automatically.

When a device enters ADMA mode, any existing endpoint state may be lost. If there is already data in the FIFO, it is reset. The current state of RX_EN and TX_EN may also change.

Clearing ADMA takes the device out of ADMA mode. DEN may clear at the same time or later. If at the same time, then all DMA operations stop immediately and the firmware must send any remaining data. If later, the device will complete any current DMA operation before exiting ADMA mode (see the description of the DSHL bit in the DMAEV register).

DTGL. DMA switch. This bit is used to determine the status of ADMA operations upon initialization. During initialization, the firmware sets this bit to "1" if it starts with a DATA1 operation, and to "0" if it starts with a DATA0 operation.

Writing this bit also updates the NTGL bit in the DMAEV register.

IGNRXTGL. Ignoring RX switching. If this bit is set, the comparison between the NTGL bit in the DMAEV register and the TOGGLE bit in the corresponding RXSx register is ignored during receive operations. In this case, a mismatch of both bits during a receive operation will not stop the ADMA operation. If this bit is not set, ADMA stops if there is a bit mismatch. After reset, this bit is set to "0".

7.2.7 DMA Event Register (DMAEV)

The bits in this register are used in ADMA mode. Bits 0...3 may cause an interrupt if they are not cleared, even if the device has not set ADMA mode. Until all these bits are cleared, ADMA mode cannot be initialized. ADMA mode automatically ends when any of these bits are set.

DSHLT. DMA software stop. This bit is set when ADMA operations are stopped by firmware. This bit is set only after the DMA engine has completed all necessary cleanup operations and returned to the idle state. Executed under the following conditions:

STAT. State. This field reflects the status bits of the transmitter or receiver selected in the DSRC2-0 field in the DMACNTRL register (DMA does not need to be active or enabled). It corresponds to TXSx or RXSx.

7.2.10 DMA Counter Register (DMACNT)

This register defines the maximum number specified for ADMA operations.

DCOUNT. DMA counter. This field is decremented as a DMA operation completes until it becomes 0. The DCNT bit in the DMA event register is then set only when the next DMA operation completes successfully. This register does not lose significance.

For receive operations, this counter is decremented when a packet is successfully received and then transferred to memory via DMA.

For transfer operations, this counter is decremented when a packet is transferred from memory via DMA and then sent successfully.

DCOUNT should be set as follows: DCOUNT = (Packet No. to be sent) -1

If a DMACNT write operation occurs at the same time as a decrement operation, the write operation has higher priority.

7.2.11 DMA Error Register (DMAERR)

DMAERRCNT. DMA error counter. In conjunction with the arithmetic error handling capability, this counter determines the maximum number of consecutive bus errors before stopping ADMA mode. The hardware software can set the 7-bit counter to a preset value. Once ADMA is started, the counter is decremented by 1 from a preset value each time an error is detected on the bus. Each successful transition resets the counter back to the preset value. When ADMA mode is stopped, the counter is also set back to the preset value.

If the counter reaches 0 and another erroneous packet is detected, the DERR bit in the DMA event register is set. Details in section 7.2.7. This register does not lose significance.

DMAERRCNT should be set as follows: DMAERRCNT = 3D (Maximum number of send attempts attempted) - 1

Write access to this register is only possible when ADMA is inactive. Otherwise, it is ignored. Reading from this register while ADMA is active returns the current counter value. Reading from the register when ADMA is inactive returns the preset value. The counter is only decremented if AEH is set (automatic error handling activated).

Automatic error handling. This bit has two different meanings depending on the current transition mode:

The area of ​​special function registers SFR (Special Function Register) of the basic MK 8051 is extensive and contains 21 registers, the purpose of which is given in table. 2.3. Their original English names are also given here, on the basis of which their mnemonic names were given.

Registers of special functions indicating the addresses and initial values ​​of the registers are presented in table. 2.4. All registers have byte addresses, but 16 of them, in addition to byte addressing, also allow addressing of individual bits. These registers are highlighted in bold in the table, and the absolute addresses of the individual bits and their mnemonics are indicated for them. Note also that these registers have an address ending with the numbers 0 and 8.

Table 2.3

The address of directly addressable bits can be written either as an expression<Регистр>.<Разряд>, or as an absolute bit address. For example, the entry TCON.2 means the address of the second bit of the TCON register. In addition, many bits of control registers have their own names - for example, this bit is called IT1.

Table 2.4

Ending table. 2.4

In Fig. Figure 2.13 shows the entire space of special function registers with their location displayed. As can be seen from the figure, the developers have built into the microcontroller architecture a very significant reserve for creating new models with expanded peripherals and functionality.

Let's look at the purpose of special function registers in more detail.

Battery A and Battery Extender B . The 8051 family of microcontrollers have a battery-centric architecture. Accumulator A is an 8-bit register that is the source of the operand and the location of the result when performing arithmetic and logical operations and a number of data transfer operations. The accumulator can perform logical operations; it also receives the results of a number of logical operations and special movement commands. Some functions are performed only with the accumulator: shifting, checking the contents for zero, etc. A special 8-bit accumulator expander register B is used in conjunction with the accumulator during multiplication and division operations to store the second input operand and place the returned eight bits of the result. In all other operations, register B can be used as a normal working register.

Despite the fact that the architecture of the 8051 family of microcontrollers is battery-centric, it is possible to perform a number of operations without bypassing the battery. Data can be moved from any cell on the chip to any register by address or indirect address; any register can be loaded with a constant, bypassing the accumulator.

Data Pointer Register DPTR . This register is designed to store a 16-bit address when executing variable move instructions throughout the entire VPD address space up to 64 KB. Consists of two software-accessible 8-bit registers DPH (high byte) and DPL (low byte), which, if necessary, can be used as independent general-purpose registers. In addition, DPTR serves as a base register for indirect addressing in forwarding instructions.

Program Status Word Register P.S.W. . When many commands are executed in the ALU, a number of signs are formed that are recorded in the PSW register. After executing the next command, some information about the result of its execution can be entered into individual bits of this register, called flags. In addition, the PSW contains flags for selecting the current bank of general purpose registers and a user programmable flag.

Stack pointer register SP . A stack is a user-defined area of ​​data memory that is written to and read on a last-in, first-out basis. The eight-bit stack pointer register SP contains the address of the last byte written to the stack. The stack is used to pass parameters between subroutines, to temporarily store variables, and to store the status word during execution of interrupt service routines.

The contents of the stack pointer are automatically decremented or incremented whenever data is written to or popped from the stack, and during calls to and returns from subroutines. Theoretically, the stack can be 128 bytes deep. The stack pointer is reset to 07H, so the starting address of the stack contents is 08H. By programmatically changing the contents of the stack pointer, you can move the stack to any area of ​​resident RAM.

When using a stack, it is necessary to take into account that the depth of the stack is not controlled by hardware, and if it increases excessively, memory cells not intended for the stack may be occupied and information in them may be lost. The hardware stack is used to store the return address when servicing an interrupt.

Parallel I/O port latches . Ports P0...P3 are bidirectional I/O ports and are designed to ensure the exchange of information between the MK and external devices, forming 32 I/O lines. The latch registers of these ports are buffer registers that store information during input and output. The purpose and features of working with ports are discussed further in a separate section.

Timer/Counter Registers . Registers TMOD, TCON and register pairs with symbolic names TH0, TL0 and TH1, TL1 are used to provide operation of two 16-bit software-controlled timers/counters. The detailed purpose of these registers will be discussed when describing timers/counters.

Serial Port Registers . Registers with symbolic names SBUF and SCON are intended to set modes and control the operation of a universal asynchronous transceiver. Their description is given in the section devoted to the consideration of the operation of UART.

Interrupt registers . The IP and IE registers are used to software enable interrupts from individual interrupt sources and change the priorities of these sources. As in the previous case, these registers will be discussed when describing the interrupt system.

Power control register PCON . Using the bits of this register, energy-saving idle and power-off modes are established. One of the bits serves as the UART baud rate doubling bit.

Concluding this section, it should be noted that with the further development of the family, registers for expanded resources of new models of microcontrollers are added to the area of ​​special function registers. For example, modern MKs include modules for additional timers, matrices of programmable counters PCA (Programmable Counter Array), watchdog timer WDT (Watchdog Timer), direct memory access DMA (Direct Memory Access), analog-to-digital converter ADC (Analog Digital Converter) and etc.

When a cashier sells a bottle of strong alcohol, in EGAIS it is taken from the balance of the second register. This rule has been in effect since October 1, 2016. As a result, if the quantity of products on the second register is zero, its balance goes into the negative, that is, at the end of the working day the cashier has a negative balance on the second register. To avoid this, you need to transfer the products from the first register to the second.

How to transfer goods

In the “My Products” section, select “Transfer to 2nd Register”, then “Transfer Products”. If the balance has not been updated for a long time, the service will do it automatically. As a result, the user will see a list of goods for which register No. 2 has a negative balance.

When making a transfer, the invoices on which the goods were received will be indicated. The system automatically selects the earliest documents, because the goods from them have most likely already been sold.

The user should check the list and click the Transfer button. EGAIS will process the data and confirm the transfer - the negative balance in the second register will be closed.

For now, the service allows you to transfer exactly as much goods as is necessary to cover the negative balance. Later, the developers plan to add the ability to transfer an arbitrary amount of goods.

The EGAIS registers are designed to store information about the remains of alcoholic products. After all, the state system monitors not only the sale of alcohol, but also data on its remains.

What are EGAIS registers

Register No. 1 is a virtual warehouse. Information about the product and its manufacturer is collected here, including certificate identifiers A and B. Register No. 1 records the receipt of alcoholic products, movement between points, return, as well as write-off and placement on the balance sheet of the Unified State Automated Information System.

Register No. 2 is a virtual trading floor. This register records the retail sale of alcohol, write-off and placement on the balance sheet of the Unified State Automated Information System.

Products with different certificates A and B, but with the same alcohol codes are grouped on the second register under one name. Let's explain with an example.

The retail outlet received 3 consignments of goods of the same name and volume from different suppliers. On register No. 1 each party will appear separately:

• Vodka “Talka” 0.5 l. 3 pcs. FB-000000000000001
• Vodka “Talka” 0.5 l. 5 pieces. FB-000000000000002
• Vodka “Talka” 0.5 l. 4 things. FB-000000000000003

When the products are transferred to the 2nd register, these products will be combined into one group. The user will see not the product code by which it will be combined, but its name: Vodka “Talka” 0.5 l. 12 pcs.

Once the product has been transferred to the second register, it can no longer be returned to the supplier, nor can it be moved to another retail outlet. When transferring, products are written off from the EGAIS balance sheet based on brief information. Whereas To return or move, you need a certificate B, but it is not taken into account in the second register.

Alcohol accounting registers

Let's consider all the paths that a bottle of alcoholic beverages can take in a store.

Receipt at warehouse

Usually the products come from the supplier. Compiled waybill, The product is placed on the first register.

Another option for admission - identified previously unaccounted products. If all the documents on it are available, then it can be recorded on the first register. If not, then to register No. 2.

Product write-off

Products are written off for several reasons.

Sales of strong alcohol. The goods are sold through the cash register, it generates a receipt and sends it electronically to EGAIS. There is an automatic write-off from register No. 2.

Sale of beer, cider, mead and other similar drinks on tap. Products must be written off no later than the next day after the container is opened. You should proceed in this order:

• after opening a container of beer and selling a certain amount of it, the entire container is recorded in the sales log;
• then a write-off act is drawn up for the entire container.

If the goods were received via invoices through Kontur.Market (EGAIS), then it must be written off from the register on which it is listed.

Return or relocation. Such operations are documented with a bill of lading. Both in the case of movement and in the case of return, the consumable TTN is sent from register No. 1. The second register is not involved in these operations.

Other write-offs - damage, loss, theft. The write-off report is drawn up manually with the obligatory indication of the reasons.

There are preferences for individual sellers - they can do not record alcohol in EGAIS if it is sold through the cash register. This applies:

1. For catering establishments where alcohol is sold in portions. On the day the bottle is opened, you need to draw up a write-off report and send it to the RAR.
2. To rural stores where there is no constant Internet access. The write-off report can be sent no later than the next day from the date of sale.

It should be remembered that when selling strong alcohol and beer drinks, you need to print Description of goods. The rule does not apply only to entrepreneurs using special regimes. They have a deferment until February 1, 2021.

Note! There are registers 1 and 2 of the Unified State Automated Information System.

Last time we considered the option of increasing the outputs of the microcontroller using a decoder chip, today we will consider a more advanced option using a 74HC595 shift register. Using just one microcircuit, you can have an additional 8 outputs at your disposal, using only 3 microcontroller legs. And thanks to the expandability, by adding a second chip, the number of outputs can be increased to 16. If it is not enough, you can add a third and get 24 outputs for use, and this trick can be repeated as many times as you like. At the same time, the number of occupied legs of the microcontroller will remain 3, beautiful!

So, let's take a closer look at the purpose of the microcircuit pins and learn how to control the 74hc595 shift register in the Bascom-AVR.

First, let's get acquainted with the outputs of the microcircuit, or rather with their functionality. Below is a clipping from the datasheet for 74hc595 with the designation of the pins of the microcircuit:

• Q0…Q7– the outputs that we will control. Can be in three states: logical one, logical zero and high-resistance Hi-Z state
• GND- Earth
• Q7′– output intended for serial connection of registers.
• M.R.– register reset.
• SH_CP– input for clock pulses
• ST_CP– data latching input
• O.E.– an input that transforms the outputs from HI-Z into operating state
• D.S.– data input
• VCC– power supply 5 volts
  

Register logic

When on clock input SH_CP a logical one appears, the bit located at the data input D.S. read and written to the shift register. This bit is written to the least significant bit. When the next high-level pulse arrives at the clock input, the next bit from the data input is written to the shift register. And the bit that was written earlier is shifted one bit to the left, and its place is taken by the newly arrived bit. The next clock pulse will write the third bit, and the previous two will move further. When all eight bits are filled and the ninth clock pulse arrives, the register begins to fill again from the least significant bit and everything repeats again. So that the data appears at the outputs Q0…Q7 you need to “snap” them. To do this, you need to apply a logical one to the input ST_CP.

- M.R. resets the register, setting all outputs Q0…Q7 to a logical zero state. To perform a reset, you need to apply a logical zero to this input and apply a positive pulse to the input ST_CP. A very useful function, since when power is applied to the microcircuit, a certain arbitrary value appears at the output. When working with a register, a logical unit must be located at this pin.

- O.E.(output enable) if a logical 1 is applied here, the outputs will be in a high-resistance HI-Z state. When we apply logical 0 to this input, the outputs will be in working condition.

- Q7′ designed for serial connection of shift registers.

But it’s better to see once than to read twice =) so let’s look at the animation:

Working with the register head-on

When mastering the work with an unfamiliar microcircuit, it is often useful to work head-on, that is, directly twitching the controls with your feet, this allows you to better understand the principles of working with the test subject. So, following the logic of the work, I wrote a program that should output the binary number 10010010 to the register output

$regfile = "attiny2313.dat"
$crystal = 1000000

Config Portb = Output

Sh_cpAlias Portb. 3 "leg for clock pulses
DsAlias Portb. 2 "data output leg
St_cpAlias Portb. 0 "leg for "latching" data into the holding register

"output through the register of the number 146 (in binary representation 10010010)

St_cp= 0 "put your foot in data recording mode

Ds= 1 "set the first bit
Sh_cp= 0 "we give an impulse to the clock output
Sh_cp= 1

Ds= 0 "set the second bit
Sh_cp= 0
Sh_cp= 1

Ds= 0 "set the third bit
Sh_cp= 0
Sh_cp= 1

Ds= 1 "set the fourth bit
Sh_cp= 0
Sh_cp= 1

Ds= 0 "set the fifth bit
Sh_cp= 0
Sh_cp= 1

Ds= 0 "set the sixth bit
Sh_cp= 0
Sh_cp= 1

Ds= 1 "set the seventh bit
Sh_cp= 0
Sh_cp= 1

Ds= 0 "set the eighth bit
Sh_cp= 0
Sh_cp= 1

St_cp= 1 "snap the entered data

End

we compile, embed into the microcontroller or look into the simulator and see our combination at the output.

It works, the sent number appears at the register output!

Working with a register in this way, although possible, is too cumbersome and takes up a lot of program memory. But it clearly demonstrates the entire methodology for working with this microcircuit. Let's consider a more suitable method.

Controlling the 74HC595 register in Bascom using the ShiftOut command

Bascom-AVR has a great team for working with all kinds of serial interfaces SHIFTOUT
This command itself will decompose the number into bit components and sequentially output them to any pin of the microcontroller; at the same time, it can issue clock pulses. Just right for working with shift registers! Command syntax:

SHIFTOUT Datapin, Clockpin, var, option

Datapin – microcontroller port for data output

Clockpin – microcontroller port for outputting clock pulses

Var – data that we want to send to the register

Option – a number from 0 to 3, this parameter selects the order in which data will be entered into the register and the active level on the Clock line at which the bit is written:
option=0 – the most significant bit comes first, Clock active level low
option=1 – most significant bit comes first, Clock active level high
option=2 – least significant bit comes first, Clock active level low
option=3 – least significant bit comes first, Clock active level high

In our case, to work with the 74HC595 register, the option parameter must be set to 1 or 3.

To latch data into a register, use the command PulseOut. This command outputs a pulse to the microcontroller leg with a specified duration. The command configuration looks like this:

Now let's output the number 10010001 (145 in decimal system) to the output of the register connected to the microcontroller according to the above diagram:

$regfile = "attiny2313.dat"
$crystal = 1000000

Dim A AsByte
Config Portb = Output

A= 145

Gosub Hc595 "we go to the data sending subroutine

End

Hc595: "data sending routine

Shiftout Portb. 2, Portb. 3, A, 1 "send data to the register
Pulseout Portb, 0, 5 "snap data
Return

Having flashed the microcontroller, you can see a similar picture; the sent combination of bits is set at the output of the shift register.

As you can see, controlling the 74HC595 shift register in Bascom consists of only two lines of code and does not present any difficulties.

Increasing the bit depth